CMOS Pipelined in-memory computing circuit for column-wise image sensor architectures

Abstract

This paper presents a CMOS binary neural network architecture specifically aimed to perform inferences on CMOS image sensors. The circuits is based on a pipelined structure which exploits the column-wise structure of most CMOS image sensors to process successive image rows at the same rate they are read from the sensor. This allows a reduction of the memory required to store the activations of the network layers. The network is composed by a first layer which performs convolutions of binary weights with analog inputs and a set of fully binarized hidden layers. This structure allows to remove the analog to digital converters in the image sensor since the first layer is able to process analog values. Hidden layers are arranged following an in-memory computing SRAM architecture: In this work, this architecture employs 8T bit cells to perform convolutions, although it can be accommodated to use other in-memory computing topologies from the literature. The proposed architecture has been synthesized at device level using a CMOS 180 nm technology to process 28x28 grayscale images. For this technology, the requirements of silicon area are reduced by a factor equal to the image height.