Modeling, design and implementation of high performance and low power dissipation pipeline analog to digital converters

Resumen

Resumen de la tesis: This thesis focuses on modeling, design and implementation of pipeline analog to digital converters (ADCs), with special emphasis on power reduction. The design of pipeline ADCs usually requires extensive simulations at transistor level. These simulations increase the overall design time. To improve the efficiency of these simulations, it is necessary to use methodologies and tools based on hierarchical descriptions, where macromodels play an essential role. Different solutions to improve the design methodology of the analog parts are presented in this work. The first proposal is based on the use of very high speed integrated circuit hardware description language for analog and mixed signal (VHDL-AMS). This language allows models of pipeline ADCs as well as for main components to be developed. Through these models, critical parameters such as capacitor mismatch or noise in the reference voltages have been analyzed. A VHDL-AMS model of a 40 MSample/s 12-bit pipeline ADC has been designed. The capacitor mismatch of each stage has been modeled and added to this VHDL-AMS model. This allowed transient simulations to be done between 200 and 700 times faster than the transistor-level simulations, depending on the tolerance of the spectre analog simulator. A second proposal describes a procedure to synthesize complementary metal oxide semiconductor (CMOS) circuit descriptions, using parametrizable macromodels. Currently, contrary to the situation with pure digital circuits, there is a lack of Computer Aided Design (CAD) tool methods for analog circuits, which facilitate completion of the synthesis flow from higher levels to silicon. In this thesis a method to perform systematic and rapid translation from a VHDL-AMS description of analog circuits to schematic level-sized descriptions is presented. Further extending the macromodeling technique, an approach for applying fuzzy logic for accurate analog circuit macromodel sizing has been developed. In this methodology, multiple adaptive neuro-fuzzy inference systems (MANFIS) have been trained to predict the performance characteristics (gain, bandwidth) of a fully differential telescopic transconductance amplifier (OTA). The neuro-fuzzy computed characteristic values were in excellent agreement and one order of magnitude faster than those obtained from device spice-level simulations. With respect to the design and implementation of pipeline converters, the influence of the OTA on the main performances of the pipeline ADC has been discussed. Two popular topologies of OTAs, telescopic and folded-cascode OTA with gain-boosting, have been analyzed in detail. For the same power consumption, the telescopic topology showed a settling time of 40% faster than the folded-cascode topology. The Telescopic topology was then implemented in a 40 Msample/s 12-bit pipeline ADC. Then the opamp-sharing technique as an efficient technique to reduce the power consumption of pipeline ADCs has been analyzed. The drawbacks and advantages of this technique have been discussed in detail. The layouts of three prototypes, with no amplifier sharing, opamp sharing in all stages, and partial opamp sharing based on a combination of both techniques, have been designed and simulated. The results showed that partial sharing had a linearity error very similar to no-sharing technique but the power consumption was reduced by 42.5%. On the other hand, full opamp sharing showed lower power consumption with a degradation of the ADC linearity by +1.77/-1.2 LSB. Based on these results, structural changes have been done in the telescopic OTA, adding an additional differential input pair. In addition, the circuitry associated to the opamp sharing technique has been adapted to work with this 4-input OTA. An additional modification of this OTA reduced the power consumption of the first and second OTA of this pipeline ADC by 24.26% and 45.23%, respectively. Finally, taking into account different stage resolutions, a 40 Msample/s 12-bit pipeline ADC without opamp sharing has been synthesized. It has shown a 18% reduction in power consumption when the topology of 1.5 bit per stage is replaced by 2.5 bit per stage. Subsequent simulations confirmed a reduction of the power consumption without degradation of the main characteristics of the pipeline ADC. Finally, a 20 Msample/s, 11-bit resolution and 2.5 bit per stage pipeline ADC has been designed. This circuit uses the opamp sharing technique and a technique that adapts the bias current of the OTA, according to the requirements of the active stage. The post-extracted simulation showed that Figure-of-Merit (FoM) and power consumption were improved by 13.5% when the adaptation of the bias current was applied. http://repositorio.bib.upct.es/dspace/