An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

  1. Diaz-Madrid, J.A.
  2. Domenech-Asensi, G.
  3. Lopez-Alcantud, J.A.
  4. Oberst, M.
Actas:
Proceedings - IEEE International Symposium on Circuits and Systems

ISSN: 0271-4310

ISBN: 9781467368520

Ano de publicación: 2017

Tipo: Achega congreso

DOI: 10.1109/ISCAS.2017.8050484 GOOGLE SCHOLAR

Obxectivos de Desenvolvemento Sustentable

Fonte de datos: Scopus