A visual simulation environment for MIPS based on VHDL

  1. J.M. Álvarez Llorente 1
  2. N. Pavón Pulido 1
  3. J. Ballesteros Rubio 2
  1. 1 Departamento de Ingeniería Electrónica, Universidad de Huelva, Escuela Politécnica Superior, Palos de la Frontera
  2. 2 Departamento de Informática, Universidad de Extremadura, Escuela Politécnica, Cáceres
Computers and education in the 21st century
  1. Manuel Ortega (ed. lit.)
  2. José Bravo (ed. lit.)

Publisher: Kluwer Academic Publishers

ISBN: 0-306-47532-4 1-280-20019-7

Year of publication: 2000

Pages: 55-63

Type: Book chapter


An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to test and study its performance. So, it is possible to join the versatility of a commercial VHDL development tool with the simple handling of a graphic environment. In addition, an assembler language has been defined to write simple applications in order to test the simulated computer.