Publikationen, an denen er mitarbeitet José Ángel Díaz Madrid (17)

2024

  1. A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

    Journal of Real-Time Image Processing, Vol. 21, Núm. 4

2023

  1. A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

    Proceedings - IEEE International Symposium on Circuits and Systems

2021

  1. Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

    Circuits, Systems, and Signal Processing, Vol. 40, Núm. 2, pp. 515-528

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

  2. Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

    Analog Integrated Circuits and Signal Processing, Vol. 105, Núm. 1, pp. 45-55

  3. Mixed signal multiply and adder parallel circuit for deep learning convolution operations

    Proceedings - IEEE International Symposium on Circuits and Systems

2018

  1. An all-hardware implementation of the subpixel refinement stage in SIFT algorithm

    International Journal of Circuit Theory and Applications

  2. FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

    2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings

2014

  1. Low-frequency CMOS bandpass filter for PIR sensors in wireless sensor nodes

    IEEE Sensors Journal, Vol. 14, Núm. 11, pp. 4085-4094

2013

  1. Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels

    International Journal of Circuit Theory and Applications, Vol. 41, Núm. 7, pp. 732-742

2009

  1. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

    Proceedings -Design, Automation and Test in Europe, DATE

2008

  1. Accurate and reusable macromodeling technique using a fuzzy-logic approach

    Proceedings - IEEE International Symposium on Circuits and Systems

  2. Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35 μm CMOS

    Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

2003

  1. An analogue current-mode hardware design proposal for preprocessing layers in ART-based neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2687, pp. 97-104

  2. CMOS analog implementation of a simplified spinal cord neural model

    Proceedings of SPIE - The International Society for Optical Engineering

  3. Current mode CMOS synthesis of a motor-control neural system

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2687, pp. 25-32

  4. Current-mode implementation of processing modules in ART-based neural networks

    Proceedings of SPIE - The International Society for Optical Engineering