José Ángel Díaz Madrid-rekin lankidetzan egindako argitalpenak (7)

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

2018

  1. An all-hardware implementation of the subpixel refinement stage in SIFT algorithm

    International Journal of Circuit Theory and Applications

  2. FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

    2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings

2017

  1. An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

    Proceedings - IEEE International Symposium on Circuits and Systems

2006

  1. VHDL-AMS model of a 40M/S 12 bits pipeline ADC

    Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2006

2003

  1. An analogue current-mode hardware design proposal for preprocessing layers in ART-based neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2687, pp. 97-104

  2. Current-mode implementation of processing modules in ART-based neural networks

    Proceedings of SPIE - The International Society for Optical Engineering