Publicacions en què col·labora amb José Alejandro López Alcantud (16)

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

2019

  1. Prácticas de circuitos y funciones electrónicas

    Universidad Politécnica de Cartagena

2018

  1. An all-hardware implementation of the subpixel refinement stage in SIFT algorithm

    International Journal of Circuit Theory and Applications

  2. FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

    2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings

2017

  1. An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

    Proceedings - IEEE International Symposium on Circuits and Systems

2012

  1. A fourth order CMOS band pass filter for PIR sensors

    2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

  2. Circuitos y funciones electrónicas

    Universidad Politécnica de Cartagena

  3. Prácticas de circuitos y funciones electrónicas

    Universidad Politécnica de Cartagena

2006

  1. Synthesis on FPAA of a smart sthetoscope analog subsystem

    Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

  2. VHDL-AMS model of a 40M/S 12 bits pipeline ADC

    Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2006

2005

  1. An approach to a VHDL-AMS library for RF component models

    Proceedings of SPIE - The International Society for Optical Engineering

  2. Description and simulation of bio-inspired systems using VHDL - AMS

    Lecture Notes in Computer Science

  3. Simulation-based low-level optimization tool for analog integrated circuits

    Proceedings of SPIE - The International Society for Optical Engineering

2004

  1. Modeling of liquid crystal tunable microwave phase shifter exploiting artificial neural networks

    Proceedings of the IASTED International Conference on Antennas, Radar, and Wave Propagation

2002

  1. Automated high level synthesis of hardware building blocks present in art-based neural networks, from VHDL-AMS descriptions

    Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 77-80

1994

  1. Automatic vision inspection system for the analysis and detection of breakages and defects of satsuma slices

    Proceedings of the IEEE International Conference on Systems, Man and Cybernetics