Publications

Ginés Doménech Asensi publications

91 results

2026

  1. A 6T - 11T In-Memory Computing Architecture for Near-Sensor Pipelined Binary Neural Network

    IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 73, Núm. 10, pp. 1036-1040

  2. An Efficient-Energy Charge-Domain Convolution Operator for CNN

    IEEE Access, Vol. 14, pp. 15713-15722

2025

  1. Fotónica de terahercios (THz): una nueva frontera donde el electromagnetismo y la óptica se encuentran

    web de la Asociación Española de la Industria de Semiconductores (AESEMI)

  2. Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs

    Proceedings - IEEE International Symposium on Circuits and Systems

  3. Optimizing binary neural network quantization for fixed pattern noise robustness

    Scientific Reports, Vol. 15, Núm. 1

  4. Vulnerabilidades en redes intra-vehiculares modernas: Un análisis de ataque de denegación de servicio sobre automotive ethernet

    XVII Jornadas de Ingeniería Telemática: Actas de las XVII Jornadas de Ingeniería Telemática (JITEL 2025). Cáceres (España), 12-14 de noviembre de 2025

2024

  1. A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

    Journal of Real-Time Image Processing, Vol. 21, Núm. 4

  2. Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods

    Circuits, Systems, and Signal Processing, Vol. 43, Núm. 10, pp. 6115-6131

  3. CMOS Pipelined in-Memory Computing Circuit for Column-Wise Image Sensor Architectures

    Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

2023

  1. A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

    Proceedings - IEEE International Symposium on Circuits and Systems

2022

  1. On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices

    Journal of Signal Processing Systems, Vol. 94, Núm. 3, pp. 293-304

2021

  1. A library-based tool to translate high level DNN models into hierarchical VHDL descriptions

    36th Conference on Design of Circuits and Integrated Systems, DCIS 2021

  2. Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

    Circuits, Systems, and Signal Processing, Vol. 40, Núm. 2, pp. 515-528

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

  2. Fixed Pattern Noise Analysis for Feature Descriptors in CMOS APS Images

    Sensing and Imaging, Vol. 21, Núm. 1

  3. High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors

    Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

  4. Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

    Analog Integrated Circuits and Signal Processing, Vol. 105, Núm. 1, pp. 45-55

  5. Mixed signal multiply and adder parallel circuit for deep learning convolution operations

    Proceedings - IEEE International Symposium on Circuits and Systems

  6. Stability and efficiency of explicit integration in interconnect analysis on GPUs

    Proceedings - IEEE International Symposium on Circuits and Systems

  7. Using Deep Learning for Defect Classification on a Small Weld X-ray Image Dataset

    Journal of Nondestructive Evaluation, Vol. 39, Núm. 3