Publications dans lesquelles il/elle collabore avec José Alejandro López Alcantud (10)

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

2018

  1. An all-hardware implementation of the subpixel refinement stage in SIFT algorithm

    International Journal of Circuit Theory and Applications

  2. FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

    2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings

2012

  1. A fourth order CMOS band pass filter for PIR sensors

    2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

2006

  1. Synthesis on FPAA of a smart sthetoscope analog subsystem

    Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

2005

  1. Description and simulation of bio-inspired systems using VHDL - AMS

    Lecture Notes in Computer Science

  2. Simulation-based low-level optimization tool for analog integrated circuits

    Proceedings of SPIE - The International Society for Optical Engineering

2003

  1. An analogue current-mode hardware design proposal for preprocessing layers in ART-based neural networks

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2687, pp. 97-104

  2. Current-mode implementation of processing modules in ART-based neural networks

    Proceedings of SPIE - The International Society for Optical Engineering

2002

  1. Automated high level synthesis of hardware building blocks present in art-based neural networks, from VHDL-AMS descriptions

    Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 77-80