José Ángel
Díaz Madrid
Ikertzailea 2009-2010 tartean
Juan Francisco
Zapata Pérez
Profesor Titular de Universidad
Juan Francisco Zapata Pérez-rekin lankidetzan egindako argitalpenak (9)
2024
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A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors
Journal of Real-Time Image Processing, Vol. 21, Núm. 4
2023
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A 12T SRAM in-Memory Computing differential current architecture for CNN implementations
Proceedings - IEEE International Symposium on Circuits and Systems
2021
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Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC
Circuits, Systems, and Signal Processing, Vol. 40, Núm. 2, pp. 515-528
2020
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All-hardware SIFT implementation for real-time VGA images feature extraction
Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382
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Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
Analog Integrated Circuits and Signal Processing, Vol. 105, Núm. 1, pp. 45-55
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Mixed signal multiply and adder parallel circuit for deep learning convolution operations
Proceedings - IEEE International Symposium on Circuits and Systems
2018
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An all-hardware implementation of the subpixel refinement stage in SIFT algorithm
International Journal of Circuit Theory and Applications
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FPGA synthesis of an stereo image matching architecture for autonomous mobile robots
2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings
2014
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Low-frequency CMOS bandpass filter for PIR sensors in wireless sensor nodes
IEEE Sensors Journal, Vol. 14, Núm. 11, pp. 4085-4094