Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees

  1. Doménech-Asensi, G.
  2. Kazmierski, T.J.
  3. Ruiz-Marin, J.D.
  4. Ruiz-Merino, R.
Journal:
Electronics Letters

ISSN: 0013-5194

Year of publication: 2000

Volume: 36

Issue: 20

Pages: 1680-1682

Type: Article

DOI: 10.1049/EL:20001202 GOOGLE SCHOLAR

Sustainable development goals

Data source: Scopus