T.J. Kazmierski-rekin lankidetzan egindako argitalpenak (2)

2002

  1. Automated high level synthesis of hardware building blocks present in art-based neural networks, from VHDL-AMS descriptions

    Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 77-80

2000

  1. Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees

    Electronics Letters, Vol. 36, Núm. 20, pp. 1680-1682