Electrónica, Tecnología de Computadores y Proyectos
Departamento
José Ángel
Díaz Madrid
Investigador en el periodo 2009-2010
Publicaciones en las que colabora con José Ángel Díaz Madrid (24)
2023
-
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations
Proceedings - IEEE International Symposium on Circuits and Systems
2021
-
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC
Circuits, Systems, and Signal Processing, Vol. 40, Núm. 2, pp. 515-528
2020
-
All-hardware SIFT implementation for real-time VGA images feature extraction
Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382
-
Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
Analog Integrated Circuits and Signal Processing, Vol. 105, Núm. 1, pp. 45-55
-
Mixed signal multiply and adder parallel circuit for deep learning convolution operations
Proceedings - IEEE International Symposium on Circuits and Systems
2019
-
A low kickback fully differential dynamic comparator for pipeline analog-to-digital converters
Engineering Reports, Vol. 1, Núm. 4
2018
-
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm
International Journal of Circuit Theory and Applications
-
FPGA synthesis of an stereo image matching architecture for autonomous mobile robots
2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings
2017
-
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation
Proceedings - IEEE International Symposium on Circuits and Systems
-
Modeling, design and implementation of high performance and low power dissipation pipeline analog to digital converters
Modeling, design and implementation of high performance and low power dissipation pipeline analog to digital converters
2016
-
A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS
International Journal of Electronics, Vol. 103, Núm. 12, pp. 1998-2012
-
Técnicas para la reducción del consumo en ADCs de topología pipeline
IV Congreso Nacional de i+d en Defensa y Seguridad DESEi+d 2016: Actas, 16, 17 y 18 de noviembre de 2016 (Centro Universitario de la Defensa (Academia General del Aire)), pp. 13-20
2014
-
Low-frequency CMOS bandpass filter for PIR sensors in wireless sensor nodes
IEEE Sensors Journal, Vol. 14, Núm. 11, pp. 4085-4094
2013
-
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels
International Journal of Circuit Theory and Applications, Vol. 41, Núm. 7, pp. 732-742
2010
-
Fuzzy logic technique for accurate analog circuits macromodel sizing
International Journal of Circuit Theory and Applications, Vol. 38, Núm. 3, pp. 307-319
2009
-
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
Proceedings -Design, Automation and Test in Europe, DATE
2008
-
Accurate and reusable macromodeling technique using a fuzzy-logic approach
Proceedings - IEEE International Symposium on Circuits and Systems
-
Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35 μm CMOS
Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
2007
-
Improvement of ANNs performance to generate fitting surfaces for analog CMOS circuits
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2006
-
VHDL-AMS model of a 40M/S 12 bits pipeline ADC
Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2006