Automated high level synthesis of hardware building blocks present in art-based neural networks, from VHDL-AMS descriptions

  1. López, J.A.
  2. Doménech, G.
  3. Ruiz, R.
  4. Kazmierski, T.J.
Zeitschrift:
Proceedings - IEEE International Symposium on Circuits and Systems

ISSN: 0271-4310

Datum der Publikation: 2002

Ausgabe: 4

Seiten: 77-80

Art: Artikel

DOI: 10.1109/ISCAS.2002.1010392 GOOGLE SCHOLAR
Datenquelle: Scopus