Publications (12) José Ángel Díaz Madrid publications

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2024

  1. A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

    Journal of Real-Time Image Processing, Vol. 21, Núm. 4

  2. CMOS Pipelined in-memory computing circuit for column-wise image sensor architectures

    2024 31st IEEE International conference on electronics, circuits and systems (ICECS)

2023

  1. A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

    Proceedings - IEEE International Symposium on Circuits and Systems

2022

  1. A Stimulator of the Salivary Excretion Based on Physical Vibration of the Parotid Glands

    Computational and mathematical methods in medicine, Vol. 2022, pp. 8252170

2021

  1. Aproximación al diseño de prácticas de laboratorio adaptativas a entornos de alta ibilidad entre la educación presencial y virtual.

    IX Congreso Internacional Multidisciplinar de Investigación Educativa 1 y 2 de Julio 2021: Libro de actas #CIMIE21

  2. Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

    Circuits, Systems, and Signal Processing, Vol. 40, Núm. 2, pp. 515-528

  3. Students' perceptions of key competencies supporting work-integrated learning

    International Journal of Engineering Education, Vol. 37, Núm. 5, pp. 1330-1342

2020

  1. All-hardware SIFT implementation for real-time VGA images feature extraction

    Journal of Real-Time Image Processing, Vol. 17, Núm. 2, pp. 371-382

  2. Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

    Analog Integrated Circuits and Signal Processing, Vol. 105, Núm. 1, pp. 45-55

  3. Mixed signal multiply and adder parallel circuit for deep learning convolution operations

    Proceedings - IEEE International Symposium on Circuits and Systems

2010

  1. Fuzzy logic technique for accurate analog circuits macromodel sizing

    International Journal of Circuit Theory and Applications, Vol. 38, Núm. 3, pp. 307-319

2009

  1. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

    Proceedings -Design, Automation and Test in Europe, DATE